Interface circuit for multiplexing multiple serial data streams from unsynchronized clock domains

ABSTRACT

A serial stream interface for combining a master serial data stream comprising a sequence of N-bit master data packets and a slave serial data stream comprising a sequence of N-bit slave data packets. The serial stream interface comprises: 1) a slave input interface comprising a slave buffer having a serial input for receiving the slave serial data stream and an N-bit slave parallel output for outputting each of the N-bit slave data packets wherein the slave buffer stores each N-bit slave data packet using at least one slave timing signal associated with the slave serial data stream; 2) a source selection circuit having a first input channel for receiving an N-bit master parallel output from a first master data source and a second input channel coupled to the N-bit slave parallel output; and 3) a serialization circuit having an input coupled to an output of the source selection circuit for receiving a selected one of the N-bit master parallel output and the N-bit slave parallel output and a serial output, wherein the serialization circuit sequentially shifts out each bit of the selected one of the N-bit master parallel output and the N-bit slave parallel output.

This application is a continuation of prior U.S. patent application Ser.No. 09/872,519 filed on Jun. 1, 2001, now U.S. Pat. No. 6,670,899.

TECHNICAL FIELD OF THE INVENTION

The present invention is generally directed to digital signal processorsand, in particular, to an interface circuit that multiplexes andsynchronizes multiple serial data streams from unsynchronized clockdomains.

BACKGROUND OF THE INVENTION

There are many applications in which it is necessary to combineunsynchronized data streams from different clock domains for subsequentprocessing by the same device. For example, in many communicationdevices (e.g., switches, routers, transceivers) a single digital signalprocessor (DSP) may be used to process multiple packet-based inputserial data streams from unsynchronized clock domains. If the inputstreams are handled separately, the DSP incurs a delay whenever the DSPswitches between domains and the input serial data stream in the newdomain is not yet completely received. Conventional solutions to suchproblems often require synchronization of the clocks in the differentclock domains.

Therefore, there is a need in the art for improved interface circuitsfor combining two or more input serial data streams from unsynchronizedclock domains into a single contiguous output data stream. Inparticular, there is a need for an interface circuit that is capable ofmultiplexing together two or more input serial data streams withoutadding special timing synchronization circuitry.

SUMMARY OF THE INVENTION

To address the above-discussed deficiencies of the prior art it is aprimary object of the present invention to provide a serial streaminterface for combining a master serial data stream comprising asequence of N-bit master data packets and a slave serial data streamcomprising a sequence of N-bit slave data packets. According to anadvantageous embodiment of the present invention, the serial streaminterface comprises: 1) a slave input interface comprising a slavebuffer having a serial input for receiving the slave serial data streamand an N-bit slave parallel output for outputting each of the N-bitslave data packets, wherein the slave buffer stores the each N-bit slavedata packet using at least one slave timing signal associated with theslave serial data stream; 2) a source selection circuit having a firstinput channel capable of receiving an N-bit master parallel output froma first master data source and a second input channel coupled to theN-bit slave parallel output; and 3) a serialization circuit having aninput coupled to an output of the source selection circuit capable ofreceiving a selected one of the N-bit master parallel output and theN-bit slave parallel output and a serial output, wherein theserialization circuit sequentially shifts out each bit of the selectedone of the N-bit master parallel output and the N-bit slave paralleloutput.

According to one embodiment of the present invention, each bit in eachN-bit slave data packet stored in the slave buffer becomes available inthe N-bit slave parallel output substantially concurrently with storageof each bit in the slave buffer. According to another embodiment of thepresent invention, the slave buffer is a first-in, first-out (FIFO)device.

According to still another embodiment of the present invention, theslave buffer is a M-bit random access memory (RAM).

According to yet another embodiment of the present invention, the slaveinput interface further comprises a slave control circuit capable ofreceiving the at least one slave timing signal and generating therefromat least one storage control signal capable of storing the each of theN-bit slave data packets in the slave buffer.

According to a further embodiment of the present invention, the sourceselection circuit comprises a first multiplexer having an M-bit output.

According to a still further embodiment of the present invention, theserialization circuit comprises a second multiplexer having a firstM-bit input channel coupled to the M-bit output of the firstmultiplexer.

According to a yet further embodiment of the present invention, theserialization circuit comprises a flip-flop circuit having an M-bitinput coupled to an M-bit output of the second multiplexer, wherein theflip-flop latches M-bits of data received from the second multiplexer onan M-bit output of the flip-flop.

In one embodiment of the present invention, the second multiplexerfurther comprises a second M-bit input channel coupled to the M-bitoutput of the flip-flop.

The foregoing has outlined rather broadly the features and technicaladvantages of the present invention so that those skilled in the art maybetter understand the detailed description of the invention thatfollows. Additional features and advantages of the invention will bedescribed hereinafter that form the subject of the claims of theinvention. Those skilled in the art should appreciate that they mayreadily use the conception and the specific embodiment disclosed as abasis for modifying or designing other structures for carrying out thesame purposes of the present invention. Those skilled in the art shouldalso realize that such equivalent constructions do not depart from thespirit and scope of the invention in its broadest form.

Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, itmay be advantageous to set forth definitions of certain words andphrases used throughout this patent document: the terms “include” and“comprise,” as well as derivatives thereof, mean inclusion withoutlimitation; the term “or“,” is inclusive, meaning and/or; the phrases“associated with” and “associated therewith,” as well as derivativesthereof, may mean to include, be included within, interconnect with,contain, be contained within, connect to or with, couple to or with becommunicable with, cooperate with, interleave, juxtapose; be proximateto, be bound to or with, have, have a property of, or the like; and theterm “controller” means any device, system or part thereof that controlsat least one operation, such a device may be implemented in hardware,firmware or software, or some combination of at least two of the same.It should be noted that the functionality associated with any isparticular controller may be centralized or distributed, whether locallyor remotely. Definitions for certain words and phrases are providedthroughout this patent document, those of ordinary skill in the artshould understand that in many, if not most instances, such definitionsapply to prior, as well as future uses of such defined words andphrases.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawings, wherein likenumbers designate like objects and in which:

FIG. 1 illustrates selected portions of the receive signal path of anexemplary radio frequency (RF) transceiver according to one embodimentof the present invention;

FIG. 2 illustrates selected portions of the transmit signal path of anexemplary RF transceiver according to one embodiment of the presentinvention; and

FIG. 3 illustrates an exemplary interface circuit for multiplexingmultiple unsynchronized data streams from different clock domainsaccording to one embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 1 through 3, discussed below, and the various embodiments used todescribe the principles of the present invention in this patent documentare by way of illustration only and should not be construed in any wayto limit the scope of the invention. Those skilled in the art willunderstand that the principles of the present invention may beimplemented in any suitably arranged amplifier.

FIG. 1 illustrates selected portions of the receive signal path ofexemplary radio frequency (RF) transceiver 100 according to oneembodiment of the present invention. RF transceiver 100 may representany conventional RF communication device, including a cell phone, awireless network card, a two-way pager, and the like. The RF receivepath through RF transceiver 100 comprises low-noise amplifier (LNA) 105,which receives an incoming RF signal from antenna 106. The RF receivepath further comprises band pass filter (BPF) 110, RF amplifier 115, RFmixer 120, local oscillator (LO) 125, band pass filter (BPF) 110,intermediate frequency (IF) mixer 135, local oscillator (LO) 140,automatic gain control (AGC) circuit 145, and digital signal processor150.

LNA 105 amplifies the incoming RF signal from antenna 106 to anintermediate level. BPF 110 filters the output of LNA 105 to removenoise outside of the desired receiver frequency range. RF amplifier 115further amplifies the output of BPF 110 by a variable amount of gaindetermined by the gain control signal AGC1. RF mixer 115 down-convertsthe output of RF amplifier 115 by mixing it with the local oscillatorreference signal from LO 125 to produce an intermediate frequency (IF)signal. RF mixer 115 effectively shifts the RF signal centered aroundthe receiver RF operating frequency down to an intermediate frequency(IF) signal.

At this point, the signal output by RF mixer 115 may have spurioussignals outside of the desired frequency range which have been amplifiedand/or introduced by the amplification steps. BPF 130 is an extremelynarrow filter that blocks all but the desired frequencies of interestfrom reaching IF mixer 135. IF mixer 135 down-converts the IF output ofBPF 130 by mixing it with the local-oscillator reference signal from LO140 to produce a baseband signal. AGC circuit 145 further amplifies theoutput of IF mixer 145 by a variable amount of gain determined by thegain control signal AGC2.

Digital signal processor (DSP) 150 receives the baseband signal streamfrom AGC 145 and further processes the baseband signal stream accordingto the type of RF communication device in which RF transceiver 100 isimplemented. In a typical implementation, DSP 150 receives multiplebaseband signal streams. For example, if RF transceiver 100 performsquadrature phase shift keying (QPSK) demodulation, DSP 150 receives anin-phase (I) baseband signal and a quadrature (Q) baseband signal.Furthermore, RF transceiver 100 may be one of several RF transceiversimplemented within the same RF communication device, such as the basestation of a cellular telephone system or a wireless local area network(LAN) card. To reduce overall system expense, the multiple RFtransceivers may share a common DSP to perform baseband processing. Ifthe baseband data streams are packet based serial data streams, there isno guarantee that the input serial data streams to DSP 150 aresynchronized or are derived from the same clock domain

FIG. 2 illustrates selected portions of the transmit signal is path ofexemplary RF transceiver 100 according to one embodiment of the presentinvention. The transmit path comprises digital signal processor (DSP)250, radio frequency (RF) modulator 205, local oscillator (LO) 210, RFamplifier 215, voltage-controlled attenuator (VCA) 220, and RF amplifier225. DSP 250 receives multiple input signal streams from one or morebaseband signal sources, such as a baseband in-phase (I) signal and abaseband quadrature (Q) signal from a baseband source and a quadraturesource, respectively. As in the case of DSP 150, if the baseband datastreams are packet based serial streams, there is no guarantee that theinput serial streams to DSP 250 are synchronized or are derived from thesame clock domain.

DSP 250 multiplexes together the input streams and outputs a combinedbaseband signal to RF modulator 205. RF modulator 205 mixes the combinedbaseband signal with a reference carrier signal received from LO 210 toproduce an RF output signal. The RF output signal is then amplified byRF amplifier 215 to an intermediate level in the range of VCA 220. VCAattenuates the amplified RP output from RF amplifier 215 and theattenuated RF output of VCA 220 is amplified by RF amplifier 225 to alevel suitable for transmission by antenna 106. The attenuation factorapplied by VCA 220 is controlled by the value of the GAIN CONTROLsignal.

FIG. 3 illustrates exemplary interface circuit for multiplexing multipleunsynchronized data streams from different clock domains according toone embodiment of the present invention. The interface circuitrymultiplexes input serial data streams from the clock domain associatedwith slave chip 305 with input serial data streams from the clock domainassociated with master chip 310. The input serial streams associatedwith master chip 310 are arbitrarily designated as the “master” serialdata streams and the input serial data streams associated with slavechip 305 are designated as the “slave” serial data streams and arereclocked with the master data streams. According to exemplaryembodiments of the present invention, master chip 310 may be a part ofDSP 150 or DSP 250. Alternatively, master chip 310 may be part of aninterface circuit that is external to DSP 150 or DSP 250.

Slave chip 305 produces two serial data streams, COUT and DOUT, thatform two input serial data streams to master chip 310. The COUT and DOUTserial data streams are synchronous with each other and with a serialclock (SCLK) signal and a serial frame strobe (SFS) signal that also areoutput by slave chip 305. In the exemplary embodiment described below,the SOUT and DOUT serial data streams comprise 48-bit words that areclocked out of slave chip 305 at a rate of one bit per cycle of the SCLKsignal. Each 48-bit word is delineated by a strobe of the SFS signal.Those skilled in the art will readily understand, however, that theselection of 48-bit words is by way of illustration only and that wordsizes greater than or less than 48 bits may also be used in alternateembodiments of the present invention.

The 48-bit serial data streams, COUT and DOUT, are serially loaded intoan input buffer stage in master chip 310 that makes each bit availableas it is received. In the exemplary embodiment, the COUT signal isstored in first-in, first-out (FIFO) buffer 320 and the DOUT signal isstored in first-in, first-out (FIFO) buffer 325. In an exemplaryembodiment of the present invention, buffers 320 and 325 may comprise1×48 bit random access memory (RAM) devices. A first strobe of the SFSsignal and a first clock cycle of the SCLK signal from slave chip 305reset index counter 315 to an address of 0 (i.e., binary value=000000)and write the first bits of COUT and DOUT into buffers 320 and 325.Thereafter, the next 47 clock cycles of the SCLK signal increment theoutput address of index counter 315 from 0 to 47 (i.e., binaryvalue=101111) and write the next 47 bits of COUT and DOUT into buffers320 and 325.

Buffer 320 has a parallel output that forms the 48-bit word,WORDC[47:0]. As each bit of the COUT input serial data stream is writteninto buffer 320, that bit becomes available at the output, WORDC[47:0].Similarly, buffer 325 has a parallel output that forms the 48-bit word,WORDD[47:0]. As each bit of the DOUT-input serial data stream is writteninto buffer-325, that bit becomes available at the output, WORDD[47:0].

WORDC[47:0] and WORDD[47:0]are applied to the input channels ofmultiplexer (MUX) 330. Similarly, two other 48-bit words, WORDA [47:0]and WORDB[47:0] are applied to the input channels of MUX 330.WORDA[47:0] and WORDB[47.0] are generated from input serial data streamsthat come from serial data sources (not shown) located elsewhere inmaster chip 310 or from serial data sources (not shown) external tomaster chip 310. MUX 330 is a 192:8 multiplexer that has twenty-four(24) input channels, each of which is eight bits wide, and an outputchannel that is eight bits wide. The 8-bit output of MUX 330 is appliedto one of the input channels, arbitrarily designated B[7:0], ofmultiplexer (MUX) 335.

Master chip 310 also comprises master clock source 345, output indexcounter 350, frame sync logic 355, and flip-flop (FF) 340. Master clocksource 345 produces a master serial clock (SCLK) signal for master chip310. The master SCLK signal clocks output index counter 350 and FF 340.For each 48-clock cycles of master clock source 345, output indexcounter 350 increments from 0 (000000) to 47 (101111) before resettingback to zero. The counter output of output index counter 350 is appliedto frame sync logic 355, which generates a master serial frame strobe(SFS) signal”once every 0.48 clock cycles. The master SFS signaldelineates each 48-bit word in the serial data stream, DATA OUT, at theoutput of FF 340.

Frame sync logic 355 also generates channel select signals that areapplied to MUX 330 and MUX 335. According to an exemplary embodiment ofthe present invention, frame sync logic 355 applies five channel selectsignals to MUX 330 that are operable to select one of the 24 inputchannels of MUX 330. Frame sync logic 355 also applies a channel selectsignal to MUX 335 that is operable to select either input channel A(i.e., A[7:1]) or input channel B (i.e., [7:0]).

According to an advantageous embodiment of the present invention, framesync logic 355 sequentially selects the 24 input channels of MUX 330such that each of the 48-bit words applied to the input channels of MUX330 are output to MUX 335 in 8-bit bytes from the most significant byteto the least significant byte. Thus, the first six channel selectsignals from frame sync logic 355 transfer the six bytes of WORDA[47:0]to MUX 335 in the following order: WORDA[47:40], WORDA[39:32],WORDA[31:24], WORDA[23:16], WORDA[15:8], and WORDA[7:0]. The secondgroup of six channel select signals from frame sync logic 355 transfersthe six bytes of WORDB[47:0] to MUX 335 in the following order:WORDB[47:40], WORDB[39:32], WORDB[31:24], WORDB[23:16], WORDB[15:8], andWORDB[7:0]. The third group of six channel select signals from framesync logic 355 transfers the six bytes of WORDC[47:0] to MUX 335 in thefollowing order: WORDC[47:40], WORDC[39:32], WORDC[31:24], WORDC[23:16],WORDC[15:8], and WORDC[7:0]. Finally, the fourth group of six channelselect signals from frame sync logic 355 transfers the six bytes ofWORDD[47:0] to MUX 335 in the following order: WORDD[47:40],WORDD[39:32], WORDD[31:24], WORDD[23:16], WORDD[15:8], and WORDD[7:0].

Each byte of WORDA[47:0], WORDB[47:0], WORDC[47:0], and WORDD[47:0] isoutput to MUX 335 for eight clock cycles of master clock source 345.During the first clock cycle, frame sync logic 355 also selects channelB of MUX 335, such that the byte applied at B[7:0] is transferred by MUX335 to the 8-bit input of FF 340. At the end of the first clock cycle,FF 340 is strobed such that the selected 8-bit input is transferred toOUT[7:0] at the output of FF 340. The most significant bit, OUT[7], iscoupled to the serial output, DATA OUT. OUT[6:0], the six leastsignificant bits of the output of FF 340, are coupled to A[7:1], theseven most significant input bits of channel A, respectively, such thata hard wired left-shift operation is performed. A[0] is hard-wired to aLogic 1. Alternatively, A[0] may be hard-wired to a Logic 0.

At the end of the first clock cycle, frame sync logic 355 selectschannel A of MUX 335 and continues to select channel A (i.e., A[7:0])for the next seven clock cycles of the master SCLK signal. During eachof the next seven clock cycles of the master SCLK signal, OUT[6:0] isleft-shifted, applied to the DATA input of FF 340, and output toOUT[7:0]. Because of the left shift operation, each of the originalOUT[6:0] is shifted out on OUT[7].

The net effect is that each of the six 8-bit bytes in WORDA[47:0] isselected by MUX 330 and MUX 335 and then is serialized by FF 340 and MUX335. Thus, all forty-eight bits of WORDA[47:0] are serially shifted outat the master serial data output, DATA OUT. This process is thenrepeated for WORDB[47:0] WORDC[47:0], and WORDD [47:0].

Advantageously, since the master input serial data streams, WORDA[47:0]and WORDB[47:0], are output first, the slave input serial data streams,WORDC[47:0] and WORDD[47:0], may be stored in buffers 320 and 325 untilneeded. In multi-chip applications, the is slave input serial datastreams may be split into multiple streams and transferred at a slowerrate to increase timing margins. Also, since buffers 320 and 325 areFIFO devices, master chip 310 may begin clocking out the beginning ofthe slave streams before slave chip 305 has completed transmission ofCOUT and DOUT to buffers 320 and 325. This provides a substantial amountof synchronization tolerance between master chip 310 and slave ship0.305.

Although the present invention has been described in detail, thoseskilled in the art should understand that they can make various changes,substitutions and alterations herein without departing from the spiritand scope of the invention in its broadest form.

1. A serial stream interface for combining a master serial data streamcomprising a sequence of N-bit master data packets and a slave serialdata stream comprising a sequence of N-bit slave data packets, saidserial stream interface comprising: a slave input interface capable ofconverting said slave serial data stream to an N-bit slave paralleloutput that outputs each of said N-bit slave data packets in parallel; asource selection circuit capable or receiving an N-bit master paralleloutput from a first master data source and said N-bit slave paralleloutput and outputting a selected one of said N-bit master paralleloutput and said N-bit slave parallel output; and a serialization circuitcapable of receiving said selected one of said N-bit master paralleloutput and said N-bit slave parallel output and converting said selectedone of said N-bit master parallel output and said N-bit slave paralleloutput to an output serial data stream.
 2. The serial stream interfaceas set forth in claim 1, wherein said slave input interface comprises aslave buffer having a serial input for receiving said slave serial datastream and an N-bit slave parallel output for outputting each of saidN-bit slave data packets, wherein said slave buffer stores said eachN-bit slave data packet using at least one slave timing signalassociated with said slave serial data stream.
 3. The serial streaminterface as set forth in claim 1, wherein each bit in said each N-bitslave data packet stored in said slave buffer becomes available in saidN-bit slave parallel output substantially concurrently with storage ofsaid each bit in said slave buffer.
 4. The serial stream interface asset forth in claim 1, wherein said slave buffer is a first-in, first-out(FIFO) device.
 5. The serial stream interface as set forth in claim 1,wherein said slave buffer is a 1×N-bit random access memory (RAM).
 6. Aradio frequency (RF) receiver comprising: a receiver front-end circuitcapable of receiving an incoming RF signal from an antenna andgenerating an amplified RF output signal; demodulation circuitry capableof demodulating said amplified RF output signal and generating aplurality of baseband serial data streams; a serial stream interfacecapable of receiving said plurality of baseband serial data streams andcombining a master serial data stream comprising a sequence of N-bitmaster data packets and a slave serial data stream comprising a sequenceof N-bit slave data packets, said serial stream interface comprising: aslave input interface capable of converting said slave serial datastream to an N-bit slave parallel output that outputs each of said N-bitslave data packets in parallel; a source selection circuit capable ofreceiving an N-bit master parallel output from a first master datasource and said N-bit slave parallel output and outputting a selectedone of said N-bit master parallel output and said N-bit slave paralleloutput; and a serialization circuit capable of receiving said selectedone of said N-bit master parallel output and said N-bit slave paralleloutput and converting said selected one of said N-bit master paralleloutput and said N-bit slave parallel output to an output serial datastream; and a digital signal processor capable of receiving andprocessing said output serial data stream.
 7. The RF receiver as setforth in claim 6, wherein said slave input interface comprises a slavebuffer having a serial input for receiving said slave serial data streamand an N-bit slave parallel output for outputting each of said N-bitslave data packets, wherein said slave buffer stores said each N-bitslave data packet using at least one slave timing signal associated withsaid slave serial data stream.
 8. The RF receiver as set forth in claim7, wherein each bit in said each N-bit slave data packet stored in saidslave buffer becomes available in said N-bit slave parallel outputsubstantially concurrently with storage of said each bit in said slavebuffer.
 9. The RF receiver as set forth in claim 7, wherein said slavebuffer is a first-in, first-out (FIFO) device.
 10. The RF receiver asset forth in claim 7 wherein said slave buffer is a 1×N-bit randomaccess memory (RAM).
 11. A radio frequency (RF) transmitter comprising:a serial stream interface capable of receiving a plurality of basebandserial data streams from a plurality of baseband data sources andcombining a master serial data stream comprising a sequence of N-bitmaster data packets and a slave serial data stream comprising a sequenceof N-bit slave data packets, said serial stream interface comprising: aslave input interface capable of converting said slave serial datastream to an N-bit slave parallel output that outputs each of said N-bitslave data packets in parallel; a source selection circuit capable ofreceiving an N-bit master parallel output from a first master datasource and said N-bit slave parallel output and outputting a selectedone of said N-bit master parallel output and said N-bit slave paralleloutput; and a serialization circuit capable of receiving said selectedone of said N-bit master parallel output and said N-bit slave paralleloutput and converting said selected one of said N-bit master paralleloutput and said N-bit slave parallel output to an output serial datastream; and a digital signal processor capable of receiving andprocessing said output serial data stream; and an RF modulation circuitcapable of receiving a processed output data stream from said digitalsignal processor and up-convening said output processed data stream toproduce a modulated RF signal.
 12. The RF transmitter as set forth inclaim 11, wherein said slave input interface comprises a slave bufferhaving a serial input for receiving said slave serial data stream and anN-bit slave parallel output for outputting each of said N-bit slave datapackets, wherein said slave buffer stores said each N-bit slave datapacket using at least one slave timing signal associated with said slaveserial data stream.
 13. The RF transmitter as set forth in claim 12,wherein each bit in said each N-bit slave data packet stored in saidslave buffer becomes available in said N-bit slave parallel outputsubstantially concurrently with storage of said each bit in said slavebuffer.
 14. The RF transmitter as set forth in claim 12, wherein saidslave buffer is a first-in, first-out (FIFO) device.
 15. The RFtransmitter as set forth in claim 12, wherein said slave buffer is a1×N-bit random access memory (RAM).
 16. A method for combining a masterserial data stream comprising a sequence of N-bit master data packetsand a slave serial data stream comprising a sequence of N-bit slave datapackets, the method comprising the steps of: converting the slave serialdata stream to an N-bit slave parallel output in which each of the N-bitslave data packets is output in parallel; receiving an N-bit masterparallel output from a first master data source; selecting one of theN-bit master parallel output and the N-bit slave parallel output; andconverting the selected one of the N-bit master parallel output and theN-bit slave parallel output to an output serial data stream.
 17. Themethod as set forth claim 16, wherein the step of converting the slaveserial data stream comprising the sub-steps of: receiving the slaveserial data stream; and storing each of the N-bit slave data packets ina slave buffer using at least one slave timing signal associated withthe slave serial data stream.
 18. The method as set forth in claim 17,wherein the each bit in the each N-bit slave data packet stored in theslave buffer becomes available in the N-bit slave parallel outputsubstantially concurrently with storage of the each bit in the slavebuffer.
 19. The method as set forth in claim 17, wherein the slavebuffer is a first-in, first-out (FIFO) device.
 20. The method as setforth in claim 17, wherein the slave buffer is a 1×N-bit random accessmemory (RAM).